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Recent content by maksya

  1. M

    Where to start learning VHDL_AMS?

    VHDL_AMS Use SystemVision from Mentor Graphics. It supports AMS.
  2. M

    where to find software for VHDL-AMS?

    VHDL-AMS SystemVision from Mentor Graphics - https://www.mentor.com/products/sm/systemvision trial version is available
  3. M

    BEST tool for fpga synthesis

    unambiguously Sinplify from Sinplicity
  4. M

    Looking for software that converts VHDL code to C code

    VHDL? SystemC? Look for C2H Compiler at www.altera.com
  5. M

    VHDL coding questions about using process and if statements

    Re: VHDL coding question This is not an irreversible accident, just syntactic error =) Point is that I wrote this code in Quick Reply window. Moreover, it was in the small hours...
  6. M

    VHDL coding questions about using process and if statements

    VHDL coding question I'm using Quartus 6.0. And neither during compilation nor simulation there are no errors or warnings. Your project is functioning correctly. IF operator in VHDL is sequential operator, and therefore you have to use it only inside the PROCESS operator. The synthesiser based...
  7. M

    VHDL coding questions about using process and if statements

    VHDL coding question What kind of problems during simulation do you mean? This project is compiled without any warnings. RTL View shows that no latches were generated.
  8. M

    Looking for info about the P1076-2007 standard

    Re: VHDL 2007 standard Unfortunately, this link is accessible only for registered users =( Can you reupload docs here?
  9. M

    Looking for info about the P1076-2007 standard

    Can anyone provide information about P1076-2007 standard? Detailed specification is preffered, but also any other documents are greeted.
  10. M

    [POLL] Program your FPGA?

    Prefer VHDL.
  11. M

    Problem with initial statement in a testbench code

    test bench problem Please post the whole code here. It is rather complicated task to answer to your question based only on this description.
  12. M

    Which fbga is suitable for 200Mhz clock, 48 pin, 4000 gates?

    which fbga alternatively look at Altera and Lattice
  13. M

    linking schematic & verilog code..

    If you have *.v file just use "create symbol from the current file" (file menu)... And also vice versa - you can generate a Verilog code from *.bdf
  14. M

    CPLD choice Xilinx or Altera

    CPLD choice Xilinx or @ltera Look at MaxII CPLD from Altera. It has internal oscillator and user-flash.
  15. M

    regarding VREF and GCLK of banks in FPGA

    1. I don't know what is there with Virtex2Pro, but always VREF pins is needed only for voltage-referenced IO standards (for example SSTL). For example in Cyclone devices you can leave these pins unconnected (or user-defined) if you use single-ended IO standards (LVTTL, etc...). But in Stratix...
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