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In my opinion, this URL could help you : VHDL/Verilog Simulation Tutorial
However, your question is not very precise. Which cadence tool you are using?
Explaining more your need is a key for members to help you.
BR,
Moez
Dear M.Mathivanan,
Have a look on the following link http://www.sourceiii.com/files/vtran/vtran_man.pdf
You could also view some examples on Source III link.
Good Luck,
Moez
---------- Post added at 09:41 ---------- Previous post was at 09:39 ----------
I forgot this link also : Source III...
Dear Ramy,
I guess it would be a great opportunity to continue Mobile Communication in field of Embedded SW Developing.
You can have a look in CES 2011, the future is very good in MC with the explosion of Tablet and Smartphones products.
Good Luck for you.
BR
Re: Questions with STIL
Hello,
Here are some answers to your questions :
1- The C statement is a condition statement where we define a default state for one or more signals. The Condition statement is used to define stimulus and/or response to be set up, but deferred from being performed...
Hello,
Your question is not very clear. But, I think that _clk is defined in SignalGroups block and contains 2 signals. _clk = 1P means the first signal of _clk group is assigned to 1 and the second to P.
Please check your STIL file especially the _clk definition.
Thanks,
Moez
Hello nabilos,
I will add some comments concerning your STIL file and some explanations.
1. Concerning the Timing block, it defines for each signal the possible waveforms by affecting it a WFC (WaveFormCharacter). This WFC will be used in Pattern block (or Procedures/MacroDefs blocks) to...
dft protoco
Hello,
I'm STIL expert in my division.
there is some error in our explanation.
You said that # is an optional parameter and this is totaly false. In the Std1450, it is written :
“ #” defines where incremental data substitution is to occur. As such, # is used to pass values into...
Hi,
I think for BIDIR pins, you can't switch directly from input to output mode (or vise versa), so the High-Z state is put to be sure that the transition is well done.
This is what I understood from the testcases I've manipulated.
Thanks and regards.
how to transfer to vcd pattern
Hello,
I'm developing pattern convertor module which translate VCD into WGL.
Send me your vcd file and I'll convert it.
Regards,
Moez
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