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For Diff pair
For the input pair that requires good matching don't apply common centroid (AB|BA technique) but do interdigitation ( AB|AB) as this will be better in matching including wiring. (I am talking specifically about this case of simple 4 transistors)
For current mirrors like the load...
Hi
Regarding your first question:
First of all, there is a feedback loop even with no load as you are connecting the output back to the input directly and the feedback factor, in this case, is one. I think that you need to check the range of the input voltage (Common-mode input range) of the EA...
For a fully differential OTA the output voltage is not well defined unless you provide another feedback loop knowing as common mode feedback loop to define the output voltage an settle to to a well defined voltage.
please check CMFB topic for more details
He wanted to multiply the current in M19 to be 5 times the current in the transistors chain
so what is done is using a unit transistor of 1.28u/300nm and in the chain a 5 transistors in series that's like multiplying L by 5
so in the reference mirror, the chan will have a size of 1.28u/(0.3u*5)...
-- If you are using a new process the first step is to check the documentation files
These files have all details about the available devices and standard voltage that can be applied and also the layout rules and so on
You can check also the devices' models to learn about physics parameters too...
You will need to evaluate the outer loop from Vout to one of the inputs (make sure it is negative)
the other input will be the reference voltage.
The effect of CM1 and CM2 -poles and feedforward zeros - will affect this loop stability and PM.
I understand that I am using virtuoso only as a framework
I mean when creating a cell view of verilog-A in library manager inside virtuoso How can I include another module inside my Verilog-A code?
Hi
I am trying to use a strobe statement to implement the attached example in virtuoso. The example is using a $strobe statement to display the output report.
I don't know how can I get this report in virtuoso?
That's what exactly I did
I created a library and cell with a view of VerilogA
then enclosed the cell with a symbol (not in this case as when I closed the project it gave me an error for the include statement)
then I a create a test cell add this symbol with voltages to test it using the ADE-L...
Hi all ,
In book Verilog-AMS he is providing an example of a listing that can use another previously developed module by using statement ' include "moduleName.vams"
I tried to use this in cadence virtuoso by copying the previous module in the same cell or even in the discpline.vams directory but...
Hi all
I am learning Verilog-A/MS now so that I can use it in modeling for blocks in cadence virtuoso. I can use it in cadence virtuoso but still, want to find other software that can be used in windows for example.
I want to ask if there are any open source software? what are the best...
Sorry for my late reply
Here you go
For M3 branch and Q8/10 branch say that the biasing current in M3 is 1/4 I8 or I10
then I3 = constant (w3/L) (VGS3-VTH)2
I8= constant (W8/L)(VGS8 - VTH)2
if you are going to desing it such that equal W/L for M3 and Q8/10 then
the VGS8= 2 (VGS3 -VTH)+VTH...
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