Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
