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Recent content by madhusudhan_prabhu

  1. M

    timing checks in testbench

    Hi All, I want to know what are timing checks in testbenches (VHDL, Verilog or System C)? types of timing checks that exists? How to implement it in any one of the above mentioned HDL languages? Thanks, Madhu
  2. M

    Binary Offset Carrier(BOC) Modulation

    Hi, I need the Basic information about BOC modulation. Can anyone help me with the some ebook, material, or any IEEE papers. Regards and Thank you, Madhusudhan Prabhu
  3. M

    TCL parameter passing

    tcl parameter passing Hi, I want to know how we can pass the parameters to a TCL file and also how we can access those parameters inside the TCL file. Ragards, Madhusudhan Prabhu
  4. M

    How can I pass parameter to a *.tcl file

    Hi, I want to pass parameter to a tcl file. e.g. test.tcl file contains: set i [lindex $argv 0] When I use the following command : source test.tcl 9 on the TCL prompt it gives an error. tcl prompt: % source test.tcl 9 wrong # args: should be "source fileName" Please somebody...
  5. M

    Features of Verilog those are not present in other HDL's

    I need information about features of Verilog those are not present in other HDL's ?
  6. M

    Verbose history of development of HDL

    I need verbose history of development HDL(Hardware description language) like VHDL, Verilog, System C etc.? Please I need some pointer(link) or document available on that
  7. M

    Digital design method other than HDL - need information

    Digital design Method Other than HDL(Hardware description Language) is there any other method by using which we can design digital circuits ?
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