Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
NF for LNA
We used the Y-Factor method as the Spectrum Analyzer we used didnt have the Noise Figure personality and the Noise Figure meter. The shift in the noise floor is measured with the Noise Source (connected to the DUT) on and off. Then using a formula, the NF is calculated. This link...
vco current limited voltage limited
Hi Saber890
With a Complementary cross coupled pair, same current generates a gmn (NMOS) and a gmp (PMOS) and hence the devices can be smaller meaning lesser parasitics. If it were a PMOS only pair which is used for better Phase Noise (low flicker) then the...
lc vco swing
Hi Saber90
Sizing of the cross coupled MOS transistors, as you may already know, has to be such that gm * Rp = 2 for sustained oscillations where Rp is the parallel resistance of the tank ckt. Once the gm value is arrived at and the current is known, use the minimum W/L to achieve...
NF for LNA
Hi
I have designed a 1.8 dB NF LNA for WLAN 2.4-2.5 GHz in 0.18 um Si CMOS. The measured NF was around 2.6 dB (indirect measurement).
Some SiGe process based LNA (MAXIM) for 2.4 GHz may have lower NF but thats a trade-off.
Regards
Maddy
**broken link removed**
Electrical parameters of the bondwire used by MOSIS's packaging vendors is listed in the site above. IPAC is one such vendor. You can get exact model of package parasitics (including pin) from their support team too.
Regards
Maddy
SiGe Technology
Advantages of SiGe are Higher fT, Lesser noise, greater breakdown voltage (useful for PA). Drawbacks are cost of fabrication, higher supply voltage--> more power consumption, "lesser integrability" (digital and analog circuits in same IC) etc. So SiGe used for applications...
Re: How to simulate a vco?
sweep your supply voltage by +/- 10% and with all other parameters fixed and see how the output frequency varies. The slope of the plot of the freq vs supply voltage gives Supply pushing
Maddy
1-dB compression point or P1-dB is also a common measure of linearity. Its the input power level at which the small circuit gain of the circuit is 1-dB lesser than the actual gain. To measure it, the input signal amplitude is swept from a small value of say -30dBm to 0 dBm in small steps and the...
How to simulate a vco?
Freq Range, PhaseNoise, Sensitivity, Supply Pushing, Load Pulling, Output power etc are some important specs. If you are using Cadence suite, cdsdoc has info on testbenches for simulating oscillator
how many transistors needed for 1 sram cell
I designed a 6T SRAM cell by referring to CMOS Digital IC Analysis and Design by Kang and Leblebici. Digital Integrated Ckts by Jan Rabaey might also be useful. Chk out the attached material. Might be of use.
Madhav
To add to Humungus's note, the no. of Monte Carlo runs to see a process spread will also be recommended by the Foundry. In an IBM process, I believe it was 30 runs. Sometimes, it may not be possible to have 100 runs in MC because of time and memory.
Madhav
Re: gm variation problem
Cant we use a constant-gm bias to bias the gm cells? I have seen it maintain constant-gm when I used it in a LNA. Just wondering... Let me know if this is wrong.
Maddy
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
