Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I know how to do with one input port to one output port.
But how about two input ports?
I need a mux to choose from the two ports.
What would be the achitecture look like?
It is one input above
Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received at port1 or port2 and deliver them in the same order at port3. Assume that each data word is 8-bit wide.
The external systems that provide data at port1 and port2 use the sender originated protocol and the...
I think you are right, but there is another problem:
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)
For 010 is C as you said, the two operation above should be add s2s1s0 or M to C, how can it be a subtraction?
And what are...
I do not know what the opcodes means.
for example, 111 stands for A, but there is no 111 in the code, how can it relate to A?
01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0)
01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory)
01 d2d1d0 110 : MOV r, M (copy memory contents...
Design a 8 bit processor with the following specifications1:
1. The processor has seven 8-bit registers A, B, C, D, E, H and L.
2. It connects with an external memory containing 32 8-bit words. The memory has a
tristate output with active low signals rd and wr.
3. It has instructions MOV, LDA...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
