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I care about it but I didn' t get your point. Now it is clear. I just don' t know yet how to implement a low pass filter for such purpose. I' ll search and try. Thank you.
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This looks much easier. I' ll try it. Thank you for the response.
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This is...
Well, I have two options as also you said (or what I understand from what you said):
- Count two sources up to 10^7 region and simply calculate the difference
- "Simply" get the frequency difference in a way and count up to ~10^3 region
I don' t want to work with such high frequencies (first...
I don't exactly know what you mean by mixer. But I' m searching for a phase detector desing in VHDL. If you know where to find one and share a link that would be awesome. thank you.
Here is latest sim. result using 1 MHz and 1.25 MHz. There is a counter connected to the output counting the rising edges of the XOR output. Expected result is 250kHz (it is the difference of two freq. inputs) but the result is 1.75 M, that's 1.75 MHz!
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It still is not clear what output...
First of all, thank you for your suggestions.
Dear Klaus,
I made some trials on Xilinx ISE 14.7 simulator and attached the result. Here I have generated two signals with 20 ms period and 16 ms period generating 16 cycle (62.5 Hz) and 20 (50 Hz) cycle respectively to match the total...
Hi guys,
I' m searching for a relatively simple way to measure the difference between two signal sources. 10MHz and 10MHz + some hundred Hz difference is subject of my issue. I' m thinking about using a flip flop for this purpose or a comparator maybe. I don't have one in my hand and before...
Hi vGoodtimes
I made some trials but didn't succeeded yet. Here is the final version of UART RX. In case of applying a half received byte, I've located another FSM to transfer the complete byte after the receiving sequence completes. But what a pity It doesn't make any sense.
I actually don't...
Maybe I should ask if we are agree about something. If we want to design a i.e 1 minute timer using 100MHz clock, we need to count 60 times until 100M-1. Here for testbench instead of 100M-1 I count until 5 and then make v_timer_seconds +1. This is just for observing the signals in a reasonable...
Hi KlausST,
Sorry I missed the section part and thank you for moving to the correct place!
Actually I don't know how I can define the problem different than below but maybe an example...
For instance:
A received byte ascii "E" means counting period of 10 secs. At first this is processed...
Hello
I'm trying to design a counter system on my FPGA board using VHDL. My design needs to receive some bytes as control signals like start, stop reset and measurement period info. For this purpose I have a UART module including both TX and RX serial lines and I'm also using a usb serial...
you mean BIST? I did it when I get the board first. But it is using some differetn software to test individual components in a seperate way.
If you talk about something different can you please provide a link?
Hi everyone
I have a KC705 FPGA board and trying to learn some basic stuff. I've checked on the int. for a starting point to write some words on the LCD screen but so far not succesfull. Can anyone suggest any useful document or a simple basic example about how to send the control bits, sending...
Hi, is there any way to do the same (similiar) thing by using crytals. Thats, a variable frequency output for example between 1-10 kHz aquare wave generator.
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