Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you for all you reply,
You mention, Vgs and Vdsat, and these voltage should referring for transistor for taken account. pls can you be more precise. to understand the entire circuit.
Hi everyone
from textbook, the schismatic as attached is class-ab, and mention the minimum supply voltage. what dose mean that, and which transistor referring by
The minimum supply voltage of the output stage equals two stacked gate-source voltages and one saturation voltage, which makes it...
Thank you for reply, but why there are splitting to capacitors, also this mention in (Compact Low-Voltage Power-Efficient
Operational Amplifier Cells for VLSI) for Huijsing
Hi Everyone :-o
Why in class-ab amplifier second stage of two stage amplifier there are two of miller capacitors or two cascode miller capacitors. I have looked to the r/r amplifier (see attachment)
:wink::wink:
Thank you for reply
I Know the structure of the op-amp but I need to know what is the relationship between phase margin and he power (or current) consumption.
Hi
I have op-amp circuit and there is changing in phase margin with different power supply.
My question is
1. why is it changing?
2. is this related to the power (or current) consumption. and How?
3. is there any reference to go back for it?
Thank you for reply,
Yes I looked to them. but I didn't Find my answer.
The problem is Tran analysis goes in wrong way. I tried to simulated as the circuit (attachment) and the result. I don't not when are the errors
Hello everyone
I trying to design Fully differential Amplifier and I am stock in Common Mode feedback circuit. what should be the gain of Common Mode feedback circuit , unity, positive or negative dB.
Thank you everyone and who has been contributed to answer my questions.
is there any disadvantages for using this particular circuit.
I need more about the Vdd/2 on non-inverting. more expansions
- - - Updated - - -
To measure the DC gain in the open loop for this circuit is the output node...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.