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Recent content by lxcpku

  1. L

    QQ group number for analog design discussion

    QQ group number for analog design issues discussion : 17359730 this group is for analog designers' communication more conveniently join in us ,right now :)
  2. L

    should bandgap voltage always be the same for same technolog

    it is said that bandgap voltage should always be the same for the same technology ? while i did not understand that ? in my design, bandgap voltage would be a litter different ,just as the bottom pic shows
  3. L

    why no compensation needed in this bandgap

    any other advice ?
  4. L

    why no compensation needed in this bandgap

    Hi,all i'd like to inquire about why Vc1 (the terminal at the output of opamp ) need no compensation ,since the output of opamp links to the the gate of the PMOS,that is two stage opamp, i think it should add compensation. anyone could help, thx a lot :)
  5. L

    help-how much my PSRR of ldo should be in my application?

    yes,the ldo is used to supply for the digital circuits
  6. L

    help-how much my PSRR of ldo should be in my application?

    Hi,all i am designing a ldo now , and it is used in a sim-card for cell-phone. that is ,battery supplies for the ldo. i wonder how much my PSRR of ldo should be in this application. anyone having this experience could help me ? it is much appreciated. thx a lot . BTW: the maxmum load current...
  7. L

    psrr issues in ldo design

    cmos ldo psrr design i am not the member of ieeeclub and can not download the thesis you suggested :(
  8. L

    psrr issues in ldo design

    ldo design psrr hi,all i have some questions about psrr in ldo design 1. if there are 3 sub-modules in my ldo , then psrr of ldo depends on the minmum psrr of the sub-module ,is that right ? 2. first i checked my bandgap's psrr. i wanna a psrr of 60db@10k,however ,in my design, only 57db@10k...
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    why input resistance at terminal +and- is low?(used in LDO)

    i run a simulation, and results shows it is a low impendance pole for sure. and it will not affect the circuit stability. but by hand calculation. the impedance at this terminal is 1/gm, which is over 100K, and fd=1/2pi*RC,which is far smaller than the simulation results. anything wrong with my...
  10. L

    how to simulate the transient respondes of LDO

    i just checked analogLib and found no VCR, can u tell me how to use VCR in details ? thx a lot :)
  11. L

    how to simulate the transient respondes of LDO

    I'd like to simulate the transient respondes of LDO when load current changes from 1mA to 20mA. but how to control the output current in transient many thanks in advance Added after 5 hours 19 minutes: it is said that it could done by control the gate of NMOS which series with resistance...
  12. L

    Bandgap with ground current is 1uA!!

    ground current is 1uA, then what's your resistance value ? i think it will be over 1M? isnot that too large ?
  13. L

    power transistor should always work in satur in ldo design?

    Re: power transistor should always work in satur in ldo desi got it ,thanks :)
  14. L

    how to get rid of pole while keep zero ?

    thx u for ur help and also i got another way to evaluate zero, that is ,as we know,there is two branches from input to output, when the current through two branches is equal,then we can acquire zero
  15. L

    how to get rid of pole while keep zero ?

    Hi,all in some application,to ensure the stability,i like to get rid of pole while keep zero . but i donot know how to achieve that. anyone could tell me ? another question: how to acquire the zero expression without deducing transfer function. thx a lot

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