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The constraints scripts constraint the design. It specify working conditions, design rules, delay information and clock information.
From my piont of view, the srcipts are the same because they are for the same design. Is there any difference?
Re: Power Analysis in DC
Hi, this is my step:
1,set link_library
set search_path
2, read_verilog (gate_level)
3, read_vcd (dependent on your testbench, extract toggle information)
4, read_parasitic
5, set constraints and other working environment
6, set_wavform_option
7, calculate_power...
What's the difference of these clocks??
(3) ideal
(4) with propagated delay.
i don't know how to express the difference between (1) and (2).
STA: static timing analyze. opposite to simulation. and it's based on paths without any input test vectors. I
CTS: clock tree synthesis. synthesis clock...
Power Analysis in DC
Hi,
for the first one, both the power values are correct. The latter one is more acurate while the first one was coming form default synthesis.
for the second one, I just do it using Prime Power. for averager power, we read asif file. And for other power, we read vcd...
I am studying the PrimePower tools for power analyze in a project. After I have finished reading the user guide, I still can not understand how to use it.
(1) After a little lab, I get some waveforms and reports. I am not sure how to analyze them.
(2) The power has something to do with VCD(which...
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