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Hi,
I have worked in power management IC design during my M.Tech. project but I am doing different job now. I would like to work in power management IC design profile in India. I have graduated in 2012. So if anyone have openings then please let me know.
Thanks,
Raju
dear saro_k_82
whatever you have discussed is true for any two stage op amp.can we have a solution to this problem. If yes please suggest me. Do you think that sub threshold region of pass transistor under light load condition creates any problem.
dear saro_k_82
I forgot to mention that I am designing an output capacitor less LDO. whatever the capacitance(Cout) showing in circuit diagram is the parasitic capacitance of the load and which I had taken it as 100 pF. So as you told, the dominant pole was at the op amp output for any load...
dear crutschow
yes. the op amp output is generated based on output voltage of LDO. when the output voltage spike is high then op amp is charging or discharging parasitic capacitor at gate of pass transistor very fast as we expected from normal LDO operation. here I have attached the output...
dear crutschow
here load current never comes to zero. my load range is 1 mA to 100 mA and during this load range I had good phase margin, gain and bandwidth. If pass transistor had not gone into sub threshold at 1 mA, LDO would have regulated the voltage properly.
dear analogbeginer
there are two cases for sub threshold operation for mos transistor.
1. when W/L ratio of transistor is changing for constant bias current: In this case if the transistor is operating in saturation region for particular bias current and for particular W/L ratio, then if we...
hi dear analogbeginer
Actually the pass transistor is designed to operate at saturation region for 100 mA of load current. so to provide 100 mA of load current, the width of the pass transistor must be too large. so when load current decreases to 1 mA, due to high pass transistor width, it is...
even though op amp has positive feed back, the overall feedback from input to output is negative feedback only. the above circuit is the basic circuit of LDO
Dear Goldsmith
thank you for your valuable response
I am designing a output capacitor less LDO..
here I uploaded my schematic.
waiting for your reply...
Dear all,
I am designing a low dropout regulator for 1 mA to 100 mA of load current. when the load current is 1 mA the pass transistor (pmos) is going into the subthreshold region and due to this, overshoot and undershoot are increased . so could you please tell me how to avoid subthreshold...
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