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Recent content by lordsathish

  1. lordsathish

    Why are RAM chips placed opposite to each other ?

    Hi ppl, I was wondering why RAM chips are placed opposite to each other i.e in the first and the last layer of the PCB. I have noticed this positioning in the PC RAM's and few embedded devices. Is there any specific reason for this ? Thanks
  2. lordsathish

    how to write Clock Gating in verilog

    Clock Gating Why do people suggest to avoid clock gating...? I came across that if we use clock gating in a module then, we'll not be able to use scan chain in that module. Is it because of that...? Thanks
  3. lordsathish

    Physical Limitations of Gate Size

    Hi Ppl, How does scaling down the gate size of the MOS cause power dissipation and data synchronization problems ? Thanks
  4. lordsathish

    output signal as input (feedback) in verilog

    Re: feedback input I'm not sure whether this will work. Try using inout. Also make it in to a sub module and while you instantiate in higher level module try to feedback the output to the input.
  5. lordsathish

    Help me design a 1001/1111 sequence detector

    vhdl code for sequence detector Ho Sorry... It should probably addressed as radjanohoun.
  6. lordsathish

    2N2222 transistor used as a switch does not work

    Re: Switch You are probably doing the wrong way. Are the signals DC or AC...? You can use a MOSFET. You can connect A to the drain, C to the source and B to the Gate of the MOSFET. I think it will work.
  7. lordsathish

    Help me design a 1001/1111 sequence detector

    verilog code for sequence detector Hi Haneet, Do you need the solution...? If so what do you want...? Just the state diagram, the digital circuit or the verilog code for it...? If you want to learn to design it by yourself then you have to learn state machines from a good Digital Electronics Book.
  8. lordsathish

    mtlab code for finding number of pixel

    thinning image matlab code Hi ammarkadir, If you want to get the skeleton of a shape, the i could suggest a simple way. You can find the distance transform, the apply a laplacian of gaussian filter to it. Its simple in matlab. It would be like this D = bwdist(BW); h = fspecial('log', hsize...
  9. lordsathish

    Difference between mod n counter and divide by n counter

    divide by n counter Hi ppl, I wanna know the difference between mod n counter and divide by n counter. that mod n counter counts from 0,1,2...n-1 but divide by n counter can count from nay value to any vale such that it has n states.
  10. lordsathish

    how write a Look Up Table

    Is the ROM for any FPGA...? Your FPGA tool, supposing Xilinx ISE must have applications(core generator) to generate it automatically...
  11. lordsathish

    clocking problem - special component to drive clock lines?

    Re: clocking problem If you think there could be skew to the clocks in the 3 FPGA's, then i guess using some synchronization like PLL could solve your problem.
  12. lordsathish

    wat is level triggering of a clock?

    Re: level triggering Why do you want to go for a level triggered latch, I guess these are the least wanted in a good logic design.
  13. lordsathish

    wat is level triggering of a clock?

    Re: level triggering Hi... Level triggering is nothing but Latches, process (enable, data_in) begin if enable = '1' then q <= data_in; end if; end process;
  14. lordsathish

    microblaze and picoblaze - help needed

    Re: microblaze and picoblaze You can follow this topic to get more idea...
  15. lordsathish

    microblaze and picoblaze - help needed

    about microblaze & picoblaze soft processor Hi... Microblaze is just a soft processor. It is'nt a tool or software. You have to use Platform Studio and EDK o implement it. You can download it from the below link. https://www.xilinx.com/support/download/index.htm I think it has 60 days trail...

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