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Recent content by lmtg

  1. L

    Power Dissipation: Virtex2 vs Virtex4

    It's exactly the same design...The inputs and logic power dissipation in V2 are the ones greater than in virtex4.. And it's virtex2pro if this makes any difference...
  2. L

    Any ideas about reducing design's setuptime?

    Really, but the set up time of the design clk??
  3. L

    Power Dissipation: Virtex2 vs Virtex4

    I used power analyzer after place and route... and virtex2 pro keeps giving less Pd :S for the exact same design.. Added after 1 minutes: rca, what you mean is not clear.. V2 works on 1.5V V5 works on 1.2V They both have an auxillary voltage of 2.5 though,
  4. L

    Design on Virtex 2 gives less Pd than when on Virtex4

    My design on Virtex 2 keeps giving less Pd than when on Virtex4 .. Ever happened to anyone??
  5. L

    Dynamic Power in XIlinx

    Hello, When considering the Pd in Xilinx summary, should we consider Vint only or the two Vaux as well?? Thanks in advance
  6. L

    Static timing report...Xilinx

    Would you be kind enough to explain to be if this sytem would work at 5.1ns or the 1.9ns the report claims to have achieved?? OFFSET = IN 1.45 ns VALID 1.9 ns BEFORE COMP "clk" HIGH; Worst Case Data Window 5.099; Ideal Clock Offset To Actual Clock 1.144; Design statistics: Minimum period...
  7. L

    Static timing report...Xilinx

    Very clear illustration, thanx : ) One more question, in the later example you gave, does this mean the maximum freq. for correct operation would be 0.9ns?? i.e. generally is fmax= s+h??
  8. L

    Static timing report...Xilinx

    I have no constraints what so ever set for my design but the static report has some positive and negative values for the setup to clk and clk to hold..What is the indication of these values and what's the difference betweenthem being + or -???
  9. L

    Power Dissipation: Virtex2 vs Virtex4

    Power Dissipation,,, I had it all mixed up, actually more power is lost in Virex 4...
  10. L

    Power Dissipation: Virtex2 vs Virtex4

    Re: Power Dissipation,,, "Clearly this doesn't take into account any other differences between the V2 and V4." What do you mean by this??
  11. L

    Power Dissipation: Virtex2 vs Virtex4

    Power Dissipation,,, Because it's supply is less..(Only 1.2V as opposed to 1.5V for Virtex2)
  12. L

    I have a problem in creating a signal in vhdl counters

    If or when would be useful,
  13. L

    error in xilinx ise. pls help my project final is this week

    Is this a syntax error??
  14. L

    Power Dissipation: Virtex2 vs Virtex4

    Power Dissipation,,, My design disspipates more power on Virtex 4 (1.2V) than Virtex2 (1.5V):S Any clues what is wrong??
  15. L

    Any ideas about reducing design's setuptime?

    Does anyone have any idea about how to reduce a vhdl pipelined design's setuptime. The design is implemented using xilinx tools.
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