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Hi yang,
if the mbist is included in the scan chain, while scan pattern includes the mbist register failed, and then we dont need to do the mbist test.
does it make any sense?
thanks
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hi, rca
yes, what i am doing now is adding an and logic to the clock select port, in...
should the scan chain include the mbist logic?
in mbist logic some registers control the clock selection.
during the scan insertion, the control registers are added to the scan chain.
and in scan mode, while shifting, the control registers' Q ports are toggling and make the clock sometimes...
waveform format
it is smaller than VCD, debugging in verdi with tb is more easy.
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waveform format
it is smaller than VCD, debugging in verdi with tb is more easy.
scan_enable is a select between SI and D,
and after shift, before capture the scan_enable is 0,
and clk have a pulse,
then scan_enable is high
and shift out.
does the scan_enable have some relation with the clk?
actually i have never seen that before.
but i have seen something using define instead.
output wire cclk_0, // controller clock output
input wire ctl_rst_n,
input wire [2 -1:0] msd_tie, // tie-hi:tie-low i.e. 2'b10...
Hi,
whole chip sdf is a must, i think.
a) if you only checked submodules, how about the interface between the modules.
b) did you take a look at the final layout netlist? it changed a lot, some high fanout pins, clk trees ,some pass through buffers and etc.
how to deal with that.
i think...
do you mean that you are coding a kind of mbist which uses the BSD to test the memories?
it sounds familiar,
some kind of tools can generate this kind of verilog, like mentor tessent
but it uses jtag IRs to shift in some instructions and shift out some results.
i think it is.
u can debug it from the unmapped points.
maybe there are some dff merged together when synthesis or some CG inserted and so on.
you need to check it.
some unmapped points can make some effect of the nonequavilent points.
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