Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have a idct C code for mpeg-4 decoder,the algorithm which used is AAN's alg
now I'm confused because this alg need only 5 multipliers when 1D process,and move the other 8 multipliers to inverse quant, the problem is, if I want to reduce the mult operation, is the other 8 mult implement with...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.