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Thanks, yes, there is OCC in my chip. Is there some other things to be done besides configuration PLL registers?
Due to the PLL needs some time to be stable after configuration, so what I should do in the ATPG patterns? waiting some cycle times ?
when I do at-speed DFT, I want to using the PLL output as refclk1 for launch and capture clock.
But there is a question, if the default PLL output clock frequency is not what I want. How can I make the PLL output clock turn to the right frequecy?
Use strap pin?
2. Can I config the PLL register...
when scan chain inserting, set edge merge enable.
Why the tool groups all trailing edge clock scan cells first and then groups all the positive edge clock scan cells?
what is the exactly reason?
1.How can I check the setup time and hold time for a timing path. the first FF is positive edge trigger, but the end FF is negative edge trigger one.
2. The hold time is still depended by clock frequency like normal?
when I using VCS to run post-layout simulation, I found some signal is High Z value in the beginning, but when I using ncverilog, there is no such issue. why?
In VCS, I found a BUF output is Z value whatever input is 0,1 or X value.There is no force or other reason to make this...
When I do ATPG, the test coverage is about 25% of some multiplier? why?
I found other multiplier test coverage is up to 99%? does bus width and signed/unsigned data of multiplier make sense in here?