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Recent content by liwei039

  1. L

    Question about PLL frequency in at-speed test for DFT

    Thank you very much. Do you have a simple testbench and PLL design or PLL documentation. - - - Updated - - - Thank you very much. Do you have a simple testbench and PLL design or PLL documentation.
  2. L

    Question about PLL frequency in at-speed test for DFT

    Thanks a lot. Can I use the strap pin for configuration the PLL? Is this a little fast than RISC to config that PLL register?
  3. L

    Question about PLL frequency in at-speed test for DFT

    Thanks, yes, there is OCC in my chip. Is there some other things to be done besides configuration PLL registers? Due to the PLL needs some time to be stable after configuration, so what I should do in the ATPG patterns? waiting some cycle times ?
  4. L

    Question about PLL frequency in at-speed test for DFT

    So, I can config the PLL register when the chip is under the scan mode. the frequency of PLL config register ck pin is scan clock?
  5. L

    Question about PLL frequency in at-speed test for DFT

    when I do at-speed DFT, I want to using the PLL output as refclk1 for launch and capture clock. But there is a question, if the default PLL output clock frequency is not what I want. How can I make the PLL output clock turn to the right frequecy? Use strap pin? 2. Can I config the PLL register...
  6. L

    One question for edge merge for DFT

    when scan chain inserting, set edge merge enable. Why the tool groups all trailing edge clock scan cells first and then groups all the positive edge clock scan cells? what is the exactly reason? Thanks.
  7. L

    how to check setup and hold-time between mixed positive and negative edge trigger FF

    Hi, shitansh, Thanks, so in this case, the hold time check is dependent on clk freq? right? Can you give me the equations for setup and hold time check?
  8. L

    how to check setup and hold-time between mixed positive and negative edge trigger FF

    1.How can I check the setup time and hold time for a timing path. the first FF is positive edge trigger, but the end FF is negative edge trigger one. 2. The hold time is still depended by clock frequency like normal? Thanks
  9. L

    [SOLVED] High Z value in post-layout simulaiton using VCS

    Hi, all when I using VCS to run post-layout simulation, I found some signal is High Z value in the beginning, but when I using ncverilog, there is no such issue. why? In VCS, I found a BUF output is Z value whatever input is 0,1 or X value.There is no force or other reason to make this...
  10. L

    Why my ATPG coverage in so low about Multiplier of design?

    Hi, all When I do ATPG, the test coverage is about 25% of some multiplier? why? I found other multiplier test coverage is up to 99%? does bus width and signed/unsigned data of multiplier make sense in here?
  11. L

    How to define an internal clock in DC?

    clock mux I just want to define an internal clock in DC. this clock is come from a mux of two input clock then through a combination logic. should be use create_generate_clock? how to use it?
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