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Problems solved! It is bcoz i use ploy1 as common plate to connect to the output. The paracitic capacitance between ploy1 and substrate is very large. For AMS 0.35, the ratio of poly1 capacitor and paracitor capacitor is about 7/1. So the total paracitic compacitance added to the output port is...
I am using cpoly. capacitors and switches are all referenced to gnd.
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Large inaccuracy problem. It is supposed to switch from 1V to 1.5V, but accutually it can only reach 1.42 V. All the capacitors and switches I use are built on P substrate. I also implemented guard...
I am working on 12-bit SAR ADC design, in which i make use of capacitor array to build DAC block. All simulations work fine in schematic simulations. However, when I did a post layout simulation on DAC block, the result is very bad. In the DAC block, I need a few switches to control the...
I am doing ADC design. In the layout design, the digital part is used standard cell and the analog part is draw by myself. But when i do the LVS check, it generated a error, "gnd! shots to gnd" (gnd! is the global ground for standard cell; gnd is the pin I created for analog part). Can any one...
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