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Recent content by LinXiaoling

  1. L

    clk sync problem for a digital communication system with two seperate parts

    Hi,everyone. Please see the system showing in figure1. System background: It’s used in wireless digital repeater including local unit and remote unit. And there are 2 different reference clocks in whole system, so it will cause the system output frequency offset badly if the 2 clocks (e.g. TCXO...
  2. L

    Digital PLL and COSTAS LOOP

    Thanks,Zerro. And until now my design based on FPGA can track CW signal,but the frequency resolution in the PLL how to be improved,I wanna 1Hz in my design,but now it is only 1KHz. And I have tried to improve it without caring locked time,but it failed.Can you give me some advice? Thanks a lot.
  3. L

    Digital PLL and COSTAS LOOP

    can anyone give me some advice on digital PLL and costas loop? can CW signal be tracked and locked in a digital costas loop?
  4. L

    CW frequency estimation in FPGA

    Hi,I have some problems in frequency estimation in FPGA.The CW signal frequency is below 200KHz at sampling about 1MHz(i.e. after DDC process).And I need to know the frequency or the equal phase increment in NCO to further my design. Can anyone give me some advice? Thanks.
  5. L

    Beacon signal for frequency correction

    Hi! I want to use beacon signal to correct the frequency in frequency translating system. But I don't have any idea about it ,can anyone give me some advise?The system includes local and remote parts. For the frequency offset,I need to adopt some arithmatic to realise it in FPGA. I'll be very...
  6. L

    How to make Verilog Code to a matlab subsystem

    use simulink for modelsim. see simulink for modelsim on matlab manual in detail
  7. L

    NCO based on CORDIC really suitable for DDC/DUC design?

    Hi! I am going to design DDC/DUC,and I have searched for some materials.And I want some experienced opinions on NCO based on CORDIC algorithms,and is it suitable for DDC/DUC design?. hope everyone can help me . THX!
  8. L

    how to implement ROM in verilog code

    Hi! I want to implement ROM (about 64*16K) in my own verilog code.and I use the code style like this: always@(posedge clk) begin if(clk_en) begin case(address) 0: ROM_data <= 16'd11; 1: ROM_data <= 16'd21; ... endcase end end but for my ROM_data is too large,so the ISE tool...
  9. L

    How can I verify my FIR design

    firdesign.pdf Hi! I have designed FIR moduel in ISE,but I have no idea about how to verify it in matlab ,simulink and modelsim(I want to check out the continuous waveform). The PDF manual has mentioned about link for modelsim,but it is still very confused to me. can anybody make some hints for...
  10. L

    Help! the material or report on DFT design for FFT chip

    Hi!Everyone. I am here for needing your help to contribute the material or report on DFT design on FFT chip . Because I have to make comparision between my DFT design and others,but It is very difficult for me to search such material. I will very appriciated for your help.Thank u! My...
  11. L

    DFT Compiler error: Bus gate xxx failed Z state ability check

    Re: DFT Compiler problem THX! my design is the top design that including bidirectional IO pads.there exists pre-dft DRC warnings on those pads.
  12. L

    DFT Compiler error: Bus gate xxx failed Z state ability check

    Hi, during the DFT design, there comes a problem:Bus gate xxx failed Z state ability check. the cause may be the bidirectional ports in the design.but I don't know how to handle it.pls help me,thx.
  13. L

    clock uncertainity in synthesis

    the max delay and the min delay depend on the block or chip next to your design .if you have no idea about it,you have to do the timing budget,usually it takes 60% of clk period .but I dont recommend this method to constrain the design,you had better know well about other blocks,then u can...

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