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insertion delay
I guess they mean clock insertion delay and clock latency.
clock latency is concept of clock tree depth before CTS, which mean a estimated value. It can be a contraint of CTS.
insertion delay mean the clock tree depth after CTS.
Re: synthesis problem
1)You can trace the path using a tools like verdi. In DC, you can use command like get_timing_path to check it.
2)It should depends on your design purpose.
3)Constraint should depends on your design purpose, but not the fondary.
I'm want to do synthesis on a design using 90G tech. I'm not sure how much timing margin should I remain for backend guys. It was 35%(including clock uncertainty) in previous design which using 130lv tech. Any suggestion?
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