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Recent content by liletian

  1. L

    is accellera UVM free?

    Hi All Is UVM free license? If so, can anyone tell me how to use it? also, if it is free, how can they make money out of it? Thanks, Brian
  2. L

    what tool and license do I need to run XILINX fpga reference design?

    Thank you for the message. Can you please recommend a evaluation fpga module board for the intermidiate level? Thank you, Brian
  3. L

    what tool and license do I need to run XILINX fpga reference design?

    I am trying to do SoC on XILINX fpga board? For example, the following reference design. https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf WHat kind of cad tool and license do I need to run the above example? Does XILINX...
  4. L

    what $finish will be sythesis to in verilog?

    so in the real processor, how do they handle this the shutdown? Thanks, Brian
  5. L

    what $finish will be sythesis to in verilog?

    Hi All For the digital computer, there always has a halt mode which basically mean to turn off the system. In the verilog, a $finish is used in verilog code. I am just wondering how the synthesizer will synthesize this to? Thanks Brian
  6. L

    What are the normal tricks to closing time in rc and encounter?

    Hi all WHat are the normal tricks to closing time in rc and encounter? maximum fanout can help. Are there other general ways to do it? Thanks
  7. L

    What does this mean in standard cell library?

    Hi all WHat does this mean in standard cell library? In here, what does 1000, 1001 mean? what is the unit? lu_table_template(delay_template_7x7) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001, 1002, 1003, 1004, 1005...
  8. L

    what is the usage of the port in the fpga?

    In general, what does port mean in FPGA? what is it used for? Thanks
  9. L

    What does this mean in RC?

    You mean generate a fake netlist with this cells ? how to observe the timing? Thanks
  10. L

    What does this mean in RC?

    how can I find the path with this cell? Is there an easy way to do it? Thanks,
  11. L

    What does this mean in RC?

    Thanks for the message. the following case is not recoverable, correct? 416373) Clock pin absent in sequential cell(s) (RSLATX4) Warning : Missing clock pin in the sequential cell. [LBR-525] : (sage-x_tsmc_cl018g_rvt_tt_1p8v_25c.lib, block starting at: 416773) Clock pin absent in...
  12. L

    What does this mean in RC?

    Hi Guys I got this info after the irun. Can anyone please explain? Thanks Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'B' and 'S' in libcell 'ADDFHX1'. Info : Both 'pos_unate' and...
  13. L

    What are the port in the digital design?

    What are the port in the digital design Hi WHat are the port in the digital design? Are they referred to input and output? How about clock? Can anyone please give an explanation or refer some documents? Thanks
  14. L

    is the race condition normally observed in RC timing analysis?

    It looks like hold time violation leads to a Race condition. how does the timing tool (like rc check the hold timing violation)? Thanks Bo
  15. L

    is the race condition normally observed in RC timing analysis?

    Yes, I think setup violation is the correct word. How does timing analysis check the setup violation. Thanks
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