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yeah ,i use divide /20 in PLL is the mixer /10 then /2 , and now verilogA module to replace the divider, the spur is normal .
and how to solve this problem?
thx!
hi,guys!
i simulate a pll with cadence spectre, and i want to measure jitter of output , someone say that cscope can do this so well , so i want to know how to take advantage of data from spectre ,and meaure jitter with cscope?
thx in advance!:-D
hi!
i design a pll:
f_out=240Mhz;f_ref=12Mhz
it ought to have spurs at 240+-12MHz, 240+-24MHz etc.
but there are spurs at 240+-6MHz, 240+-18MHz too, i dont know why!
**broken link removed**
hi guys!
i design a pll (verilogA), 12MHz input , C2=400p, C1=40p, R2=3.3k，bandwidth＝600k，Kvco＝600MHz/v，Icp＝20uA，when locked , the wave of Vctrl is as follows, why the Vctrl like this? i don't think it is ripple.
But when i delete divider, this condition will not occur, but the divider is ideal...
what's the kind of packaging is it?
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Thanks in advance
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