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I really appreciate for your post,and Due to the poor English description,i stop it.Fortunately,last two week,i fixed out this problem ,it's about timing constraints , at the beginning i have a bad Timing Closure in my system and make it unstable.
HI friends!
I copied the two FPGA projects ,One project signaltap I added two signal under test, another project I added three groups of signal under test. in both projects I were a group of the measured signal is a particular concern to me, but the end result output the signal of interest is...
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