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Recent content by liangshangquan

  1. L

    LOW SFDR IN DIFFERENTIAL DAC

    differential dac vijayviswam:i have question.How do you get the result of the 3rd harmonic?
  2. L

    VCO tuning range plotting

    set a variable to a node ,sweep the trans
  3. L

    Does verilog_xl support verilog2001?

    Does verilog_xl support verilog2001? I have tried it by modelsim,but does not kown if verilog_xl supports it or not.
  4. L

    How to generate clock signal by PLL for FIR?

    Thanks.
  5. L

    How to generate clock signal by PLL for FIR?

    I have a task to simulation a FIR which is the circuit level. it has four clock signals which come form PLL. my tutor asks me deisgn an ideal PLL model which could provide the clock for FIR.
  6. L

    how can I run this example

    I also do such a project. Now my task is to simulation our Interpolation FIR filter. Would you like to comumicate to me. my email is liangshangquan@163.com Could you give me your example of you downloard. Thanks!
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