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Recent content by lghhust

  1. L

    nonlinear error measurement in analog multiplier

    nonlinearity error measurement Could any one help me to measure nonlinear error ? thanks[/img]
  2. L

    sense several microvolt,who can help me .3q

    it is about 50 meg; I don't regard this important ,because my problem is to amplify a uv volt to about logic 1 or 0.Of course, this op is followed by some turning circuit.
  3. L

    sense several microvolt,who can help me .3q

    thanks. I need to sense a difference of several uv,and turn it to "1" or "0", thus , I need an op with more than 100dB,to gain low offset and better noise performance , I have to chose bjt say npn or pnp as input pairs,and add additional stages.I use the form of simple 2 stages cmos op,but...
  4. L

    Help on Simulation on HSPICE

    I think it works,if only add some options such as ".option node list post........" In your case so far as I know, no pic will be seen.
  5. L

    sense several microvolt,who can help me .3q

    yes,that's right.What I need to do is to amplify a uv signal to a logic voltage.The first stage of course is used to generate a uv difference(sorry for further detail ),then amplifier is needed to amplify this signal ,and followed by a shaping circuit,which turn a weak pulse to a clk.
  6. L

    sense several microvolt,who can help me .3q

    It's a part of clock generator.However,the forward stage only provide a voltage difference about several microvolts,it's differential,thus no voltage reference is needed. The block in front of me is how to find out a circuit which can solve this tough problem.
  7. L

    a question about dc simulation in cadence.

    it's hard ,so far as I know.Use parametric simulation only provide you the same result as a diode connection simulation
  8. L

    sense several microvolt,who can help me .3q

    I want to sense a volt with only several microvolt difference,ordinary op sucks,who can give me some advice , thanks very much
  9. L

    Low Voltage Rail to Rail op,who could give me some advice ?

    thanks a lot! the |Vth| in my circuit is about 0.4. I biased imput diff pairs in weak inversion and it appaered that a zore is in RHP at about 1M, I felt frustrated and don't know what's the reason. To yschuang It might increase mismatch by using pmos and nmos input pairs togather,so I use...
  10. L

    Sub-threshold saturation--is that ok?

    gm=I/(nkt),so gm may be nearly constant,that's why Gain &PM remain the same.
  11. L

    cadence questions regarding analogLib

    cadence questions Yes.that is only a symbol, it's parameter is determined by you process file,e.g. SIMC process file.
  12. L

    cadence questions regarding analogLib

    analoglib include cadence You can use ncsu-design kit,you may download and ues this one. Besides ,analogLib is ready to use when you successfully install cadence.
  13. L

    Low Voltage Rail to Rail op,who could give me some advice ?

    bulk driven may cause lager gm variation,though get lager input range.I will find if there is any way to compenstate this variation. thanks a lot!
  14. L

    Low Voltage Rail to Rail op,who could give me some advice ?

    I am designing a low voltage(below 1 Volt) rail to rail op,and the veriation of that op needs to be kept in 5% in the whole supply range ,could anyone geive me some advice? thanks a lot.
  15. L

    problem in installing hspice 200503 in redhat

    ent 4 I have installed 200409,it worked well.
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