Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by LethalCorpse

  1. L

    [SOLVED] altium 14.3 autosaves removed? [solved]

    altium 14.3 autosave removed? Lost a day's worth of work because I forgot to save like an idiot. Thought I'd turned on the autosave long ago, but clearly not - my history files only contain manually saved revisions, and nothing since the 22nd on these files. So I went to turn on the autosave...
  2. L

    Thermal via questions

    I've been thinking a lot about thermal strategies and when and why to use or not use thermal relief. A very good discussion on the subject happened here, but the forumbot suggested thread resurrection was a bad idea, so here I am. Do you use thermal relief on the thermal pad of high power...
  3. L

    Altium KeepOut but not Rout

    I need to define areas where nothing will be placed, including polygon pours, but which don't get routed. The keepout layer works perfectly on the screen, but the manufacturer will rout big holes in my boards. I thought I could do it with a mech layer, but I can't define clearance rules for...
  4. L

    Altium: applying rules to polygons on mask layers

    On a related note, there are two conflicting goals with the design of the heatsink - one needs to maximise the heat transfer during operation without making it so good that the pad can't solder during reflow. Our fabricator doesn't have an x-ray machine, so we can't tweak the reflow profile much...
  5. L

    [SOLVED] How to create a footprint with thermal pad & tented thermal vias in Altium Designer

    Re: How to create a footprint with thermal pad & tented thermal vias in Altium Design I discovered a bug with this, or at least a significant problem. I found it's possible to see exactly what your mask will look like without going into the gerbers by using 3d mode with the colours by layer...
  6. L

    Altium: applying rules to polygons on mask layers

    Thanks for that - I was wondering how the hell to meet the chip mfr requirement that the vias be tented on the top to prevent thieving, and with your guide I've got that sorted. I've worked around my problem by making the bottom layer poly put octagons around pads instead of arcs, which let me...
  7. L

    Altium: applying rules to polygons on mask layers

    I've got a component which requires a fairly hefty heatsink pour on the bottom layer. Next to it I've got a couple of high voltage traces that I want to keep well clear of the heatsink polygon. I want to make the poly as big as possible, so instead of manually stepping around the traces in...

Part and Inventory Search

Back
Top