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Recent content by LeoK

  1. L

    Is it possible to read-back from an already programmed FPGA?

    Yes, Use EXAMINE operation for Altera devices in Quartus or Readback operation for Xilinx devices in iMPACT.
  2. L

    I would like to know function of boundary cells

    You can read here. And here.
  3. L

    Downlaod odb++ viewer

    You can try for free StarTest JTAG Manager. It also works like a CAD viewer and reads ODB++.
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    Adding JTAG interface to custom board

    By the datasheet the JTAG/SWD pins are: JTMS/SWDIO - pin 72, port PA13; JTCK/SWCLK - pin 76, port PA14; JTDI - pin 77, port PA15; JTDO - pin 89, port PB3; NJTRST - pin 90, port PB4.
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    Combined GUI for JTAG testing and CAD viewing.

    StarTestTM "JTAG Manager" software is a combined GUI for JTAG test sequences running and Board Under Test (BUT) layout CAD viewing in connection with BOM and Schematic PDF of the BUT. This configuration allows visualization of the test process and provides fast searching of the BUT objects...
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