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Recent content by LeeYan

  1. LeeYan

    IBIS model dv/dt data , how does it deifine?

    emm...during these days I had read your cookbook all finished, and delved into it. the book you recommanded is great. I know you tend to forget the theories, so thanks all the same. the question was not so important already , coz I know it is neglected by the simulation tool , through my...
  2. LeeYan

    PCB cutout in a BRD file using Cadence Allegro

    but how do you use this cutout file? usually layout is import from schematics, when your new design is completed, once you import it, the cutout part is removed. you should "cutout" schematics first
  3. LeeYan

    IBIS model dv/dt data , how does it deifine?

    thank you for your reply ! I know the definition of rise time, but I dont know about "IBIS uses 20-80%" , the "20-80%" is the time or the voltage ? you may think about a kind of waveform, if it is not a quite linear , "20-80% time" is not equal to "20-80% voltage" your handbooks are helpful for...
  4. LeeYan

    IBIS model dv/dt data , how does it deifine?

    here is a part of the IBIS model of "DM9000C" IC [Ramp] | variable typ min max dV/dt_r 1.72/0.86n 1.20/1.13n 1.96/0.66n dV/dt_f 1.76/0.79n 1.36/1.01n 2.00/0.74n R_load = 0.50k does dV/dt 20% mean 80%...

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