Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
NBTI
It is the generation of interface traps when stressed at negative voltages... it is believed to be due to the reaction between cold holes and the Si-H bond at the interface...it is more in pmos devices
Hi,
I have a doubt in razavi's book. It is in Switched capacitor chapter pg 425. Here he says if switch s1 is open then the voltage at Vp and Vx goes to infinity if the capacitance from node vx to gnd is zero.
Also he says if cx is the capacitance frm Vx to Gnd then both Ch and Cx will carry...
I am not able to understand how does STI and dual gate tech help in this regard,,, If we put a contact on poly on the active area... the possibility of contact etching penetrating the poly still remains...
In MOS Length Increased Vth decrease ????.. Think it is as the length decreases as the S/D come closer... There would DIBL effect... and also due to charge sharing.. The Vt decreases...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.