Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi, I am trying to make a pulse generator with conditional delay.
But it is not working.
Can someone help me with this?
module verilog_pulse(out);
output out;
electrical out;
parameter real fpul = 500M;
parameter real fsin = 242M;
parameter real vdd = 0.8;
parameter real t_tran = 0...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
