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Recent content by learnbydo

  1. L

    What basis floorplanning has to be done?

    Eg. * Determine the location of large block * Macro placement, such as RAM, HardIP, analog block ... * Determine the location of IO pad * Power topology selection
  2. L

    How to write test cases in Verilog?

    Verilog Test cases First build verification environment which contain tasks Then write testcases based on it and call the task <writing testbenches> is a good book about verification. It may be helpful to you
  3. L

    Why 1K boundary is used in AHB Bus ??

    ahb burst 1 kb boundary one purpose is to avoid across two slaves in one transfer
  4. L

    Reg: Need for Synchronizer

    If the target register is the flip-flop trigger by clock edge, I think it is no need synchronizer. I am uncertain in the case of latch.
  5. L

    Which is easier to code: logic which works on clock or logic which is combinational?

    Design register your output if there is no need to optimize. this will make the circuit easy to integer with other part of design
  6. L

    Problem with initial statement in a testbench code

    test bench problem Because this statement is only execute once at the start of simulation. your design is not prepare the correct value on the simulation time 0.
  7. L

    Initial Statement in Verilog: Blocking or Non Blocking

    Initial Statement I think non-blocking is better. All variable is assigned at the same simulation step.
  8. L

    Explanation of Static Timing Analysis

    STA It is said as static because the timing information is obtain through calculation, not by simulation STA analysis the delay of all paths register to register, input to register, register to output and check if there is a violation if the delay of one path is too large, there will be setup...
  9. L

    Question about Verilog RTL syntax

    Verilog RTL syntax I think it is no difference to synthesis tool. But i am prefer : always @( posedge clk_i ) begin game_a_0 <= game_a_i; end always @( posedge clk_i ) begin game_b_1 <= game_b_i; end Only one variable is assigned in one always block
  10. L

    cross module refrance

    cross module reference: hierarchy reference to the signal in another module such as top.sub1.data
  11. L

    Help me start designing an UART from APB

    About UART Design First read the specification of UART and be familar with the timing. Then think the hardware architecture and memory map registers. state machine can simplize you thinking but may not be the best way. you can try shift register + control logic
  12. L

    Anyone use Synopsys's Systemverilog VMM?

    vmm + modelsim I use ncverilog and many syntax can't use such as virtural interface, global level class declaration ... I think VCS is better for SystemVerilog. I believe SystemVerilog is the trends for verification in the future. But i don't know any commecial tool implement VMM base class.
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    Advantages of SystemVerilog compared to NCVerilog ???

    SystemVerilog is an language which is most usually used for verification today. Some syntax of SystemVerilog can't used when use ncverilog simulator. VCS is another good choise when choose simulator
  14. L

    What's the best VHDL/Verilog/SystemVerilog editor?

    systemverilog emacs vim I like vi It is simple and powerful The keyword can high light display The keyboard is enough and no need to use mouse
  15. L

    Simple verilog question

    I think it is in race condition The result is uncertain Phehaps dependent on simulator or the context of simulation
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