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Recent content by ldhung

  1. L

    Interface Logic Model in Synosys is obsolete

    the create_ilm command is no longer support (OBS-030)
  2. L

    Interface Logic Model in Synosys is obsolete

    Hi there, As I know, the command to create Interface Logic Model (ILM) create_ilm in ICCompiler 2017 version was obsolete. Do you know that is there equivalent command to substitute for create_ilm, or the functions of ILM are completely removed and are already included in CEL view an FRAM view...
  3. L

    Encounter license error

    Hello, I installed Virtuoso 6.14 and worked fine, and now I go on installing SOC Encounter 62 But when start to run command "encounter", the following error: This version requires license using cdslmd daemon Checking out Encounter license ... Fail to find any Encounter license... Please check...
  4. L

    hspice.ini not found in CIW virtuoso

    Hello, When I run Virtuoso, there is one error in CIW window like that: *Error* load: can't access file - "/home/eda/cadence/ic614.hotfix/tools.lnx86/dfII/home/eda/synopsys/hspice_vE-2010.12/hspice/hspice.ini" DO you know how to fix it, how can we configure location of hspice.ini to avoid this...
  5. L

    Timing violation in PrimeTime

    Thank you, yx.yang, As your mention, in my case, there are timing violation due to design rule. This is a result after running IC Compiler. In case that slack values are less than 0, we can use fix_eco_timing and write_changes to generate ICC TCL to fix, but in report timing file there are no...
  6. L

    Timing violation in PrimeTime

    I did timing verification with PrimeTime. After the report_constraint, there are some violations as below **************************************** report_constraint -all_violators -verbose Pin: U18129/Y max_capacitance 0.33 - Capacitance 1.01...
  7. L

    [SOLVED] IC Compiler cell is locked by ...

    I deleted all the .lock file in all subfolders. It is OK now.
  8. L

    [SOLVED] IC Compiler cell is locked by ...

    Thank you for your quick reply. I deleted the *.lock in the milkyway library. However, I still have encountered this same problem.
  9. L

    [SOLVED] IC Compiler cell is locked by ...

    Hello, I have encountered an error with IC Compiler. When I open a cell from a library, there was an error: "cell is locked by pcname (pid 1234 server) check again ..." I run command ps to list the thread and try to use command kill 1234, but the pid 1234 is not available. Please help me how to...
  10. L

    net can not connected in IC Compiler

    Hello, I have encountered a problem with ICC routing. Some nets are not connected and therefore can not route to IO pins. Please see the attached photo. Please help me point out this problems. Thanks
  11. L

    Create .LIB from .CDL

    Hello, Does anyone know how to generate .LIB file from .CDL files using NCX Liberty step-by-step? Thank you
  12. L

    HVH and VHV routing in IC Compiler

    Thank you so much. Do you know exactly the keywords in VIA ?
  13. L

    HVH and VHV routing in IC Compiler

    I want to change the VHV (Vertical - Horizontal - Vertical) routing styles to HVH (Horizontal - Vertical - Horizontal) routing styles in IC Compiler. How can I modify ? In technology file ? Thank in advance
  14. L

    hierarchy design in IC Compiler

    I did, but the ICC informed that the cells are misplaced or placed nor correct.
  15. L

    why input in @always not synthesizable

    When I synthesize the code in Design Compiler, input matchen; input conditions; input [NUM_WORDS-1:0] ss1, ss2, ss3; output reg [NUM_WORDS-1:0] match_onehot_addr; always @(matchen) begin if (conditions) match_onehot_addr <= ss1 & ss2; else match_onehot_addr <= (ss1 & ss2 &...

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