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Recent content by layoutmaster

  1. layoutmaster

    poly width Vs current density

    poly width It's highly dependent on your process. For instance, we work with processes where (depending on the metal) our metal current densities are 2 to 15 times the density you mentioned... In order to avoid problems, I recommend you to get the data directly from the foundry owner of your...
  2. layoutmaster

    Why we put a Boron implant / Salicide blockage layer on ESD structures?

    ESD Layout Actually, it's Silicide and not Salicide. The silicidation is used to reduce sheet resistance for instance in POLY and also in Source and Drain difusions, in order to reduce the parasitic resistance. IN the ESD case, and that's correct from K-90 post, by blocking the silidication...
  3. layoutmaster

    Why does metal2 shold be vertical ?

    It's not a requirement at all, but when you are designing a complete chip and you need to route toplevel signal lines you'll need a neat and ordered routing both in the chip toplevel and the lower hierarchy blocks to make your life easier and get things done on time...
  4. layoutmaster

    Layout error: the minimum overlap of M1 ground plate to LSM is 10um.

    layout error I´m not saying you can't do a single 1pF cap. Probably the DRC error was based on how the cap was made (as soon as in one direction you have an overlap between metals below the required 10um, you'll have the error) With my comment, what I was trying to say was that, if your...
  5. layoutmaster

    ESD Layout and Design Rule Checker

    esd check tool Every big company has automated rule checker as stated by you..., anyway I'm not sure they're able to check ESD rules for real, you can just check some rules that will drive you to a safest position but real ESD check... don't think so...
  6. layoutmaster

    How to properly do chip floor planning?

    Chip Floor planning Just to avoid typing the same again and again, make a search on this same forum about Floorplanning, I remember at least 2 or 3 topics where I gave my comments and recommendations about Analog chips Floorplanning. In addition, I would recommend you to read Alan Hastings...
  7. layoutmaster

    Layout error: the minimum overlap of M1 ground plate to LSM is 10um.

    layout error By following standard DRC jargon, I would say that M1 ground plate MUST overlap your LSM in at least 10 um and you're having an overlap that's smaller than that... To correct that you must draw an overlap of layer bigger than 10um. I don't know your CAP/AREA but probably you'll...
  8. layoutmaster

    How to connect copies of a cell in series using Virtuoso?

    virtuoso question If what I understand is right, you're trying to modify a parameter of cell that's two levels of hierarchy bellow... I'm not sure if you'll be able to do it. I never saw something like that. I never needed to do it so I never thought if possible...
  9. layoutmaster

    How to connect copies of a cell in series using Virtuoso?

    virtuoso question You do not need an script for that... you can get it by just doing the following: 1- Create the unit cell in such a way that, if you put two of them side by side, they get connected. 2 - Make a "Copy" and, in the copy pop-up menu, put 99 in the column or row field... You'll...
  10. layoutmaster

    Matching of capacitors in a DAC

    So, what I understand from your post is that you'll be using MiM caps (Metal-Insulator-Metal), in that case, the grounded grid I'm suggesting should be done also with metal...
  11. layoutmaster

    Matching of capacitors in a DAC

    1) What is a good idea is to set a unit cell that allow you to create all the set of caps...don't run away from this choice, it's the correct one. 2) The problem is the huge leap between your smallest and your biggest cap, there's no alternative, your unit cell MUST be 1fF... 3) From what I...
  12. layoutmaster

    are these layouts manufacturable?

    quaternion, That's correct, MOS transistors oriented in the same direction match better than those with different orientation due to the anisotropic nature of monocrystalline silicon.
  13. layoutmaster

    why we me must make a dummy for matching

    Dummy All the previous posts are correct... Basically what you want is to have all the components that need good matching under the exactly same conditions, that's why, in order to avoid possible process etching effects in the border components, you place dummies in order to have them...
  14. layoutmaster

    Introductory materials about floorplanning

    floorplanning Tan, It depends on which world you use to work and design... Probably in the Digital world is not that critical to do a chip floorplan and you can rely on automatic tools for doing it, but as an Analog-Mixed Signal design engineer with more than 10 years of experience, an a lot of...
  15. layoutmaster

    the width of guardring

    I agree with one of the very first posts... Except on very particular cases, the width of the guard ring is not important, the most important thing would be to have it there and having the correct depth and functionality. What I mean with this is that, usually, rings are there just to collect...

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