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Recent content by laydesign

  1. L

    Is it necessary to do post layout simulation after STA?

    if you want to find the "Timing violation" , i think no need! if you want to find the "behavioal error " , i think yes !
  2. L

    ESD question about protection circuit at the output

    Re: ESD Question The output MOS width + the ESD MOS width fit the ESD current discharge ability . If the Output mos width is big enough , You don't need esd . If the output mos width is not big enough , add the following mos width with the extra ESD structure . best regard!
  3. L

    Measuring angle in Cadence Virtuoso Layout Editor

    use divaExtracRules( offGrid("LayerName" raw GridValue) ) find the offgrid layer , anyAngle figure is offgrid in common . or you can write skill function to check !
  4. L

    Dracula DRC failed: Could not check out DRAC2CORE (2) 1.000000

    Re: Dracula DRC failed PDRACULA LICENSE have not been active.
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