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Re: How to design a LNA ?
Hi If you are using CMOS
Try to check Thomas Lee's book, I remember there is a very good example, also his paper about add Capacitor between gate and source.
Some golden hints!
1. Do not consider old (10years) textbook designs
2. Set a fixed gain for stage ~12dB
3. Mimic a load resistor with a PMOS in linear mode
4. Make shure that the PMOS remain in linear over input range
5. Set up a replicate bias for the PMOS load
6. Use local AC coupling...
I started my Ms Thesis last week, the title is CMOS limiting Amp. but the specification is not clear yet, I just knew I shall design a CMOS limiting amp, software is cadence, 0.13u process. I download about 90 IEEE papers, I am still in reading stage, shall I start to do some cadence exercise...
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