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i agree with timing critical nets. but this design was meeting timing and had a positive slack and had a huge area. i have a 570 ns positive slack so i thought removing buffers will help optimize the design.
Hey English Dogg,
Thanks for the quick help. it was a debugging issue and i never worked wit RC Compiler before, hence i did not know the work around for it. But now that u say, i will spend time reading the document thoroughly before i make any more posts regarding the doubts i have.
Once...
Thanks for helping me out with my previous question.
I'm having difficulty to create a structure in RTL compiler.
i m using the edit netlist command .
i need to create a structure with 4 ip ports, 1 drives a buffer pair which goes into a nand gate whose other input is port 2.
port 3 is...
The reason is , after synthesis i see about a 7000+ buffers in design, which is a significant area number/power number, so i was wondering what is the optimized area for the design w/o buffering.
I'm not trying to make it match any timing for now, but i'm looking at options for reduction of...
Thanks Guys !
That Helps !! I also wanted to find the Buffers in the Design. I'm using RTL Compiler RC 11.0 , After synthesis, (incremental) - i need to find the buffers n remove them - is there any such command for that??
After synthesizing the netlist - i want to use the find command to find the flip flops in design, buffers , latches etc in the design. How to get this information in RTL compiler ??
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