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You can increase it to what ever value you want. The width (parameter) can probably only go up to a fixed value (depending on the technology you use e.g. 200u), after that you will have to use the multiplier to "increase" it.
At the end you pmos should be in the milimeter range.
Try a 10mm wide...
subbu2, you have to increase the size of the pmos transistor VERY much in order to support 50mA of current.
You cannot expect this circuit to work correctly using a 10u/0.18u mosfet.
You can check if the layout view has the thick oxide layer.
You can find which layer this is by cross checking the layout of thinoxide and thickoxide pmos devices.
It would be better if you used an external opamp integrator instead of a simple RC.
The RC might work well only if your input signal is very small and centered at Vdd/2. In other case your "integrator" would be a RC charge/discharge curve, not a straight line.
Hello,
First, your problem has nothing to do with common centroid. LVS cannot understand if you used such a technique.
1)Using multiplier must give you multiple objects. I have not encountered this before. Generally I use a mix of multiplicity and fingers.
2) You haven't connected the bulk of...
There is no way for me to know what metal layer is the purple one, I don't have this technology.
You should check you tech documentation.
Maybe "Design -> tap" can help you. Use Tap and select the capacitor metal. The appropriate metal should be chosen automatically at the LSW window.
I cannot help you with the design issues. You should consult your text books.
I cannot see the layout picture, it doesn't matter thought. You should check the documentation of your technology for any special rules.
You have to do: Results -> Direct Plot -> Main form -> noise analysis. Then choose noise figure and press plot. It will plot the NF in dB.
For the Output/Input noise you can choose the units you prefer.
1. You can choose the unit in the main form panel. If you don't know what it means, check any analog design book and read about noise.
2. Noise figure is already given in dB when you plot it. No analogLib component has a layout view. You don't need it.
Using the method of the first link, if you replace V1 with a port (analogLib -> port) and set it as the input port for input noise simulation (at the noise analysis options) then it will also calculate the noise figure.
You can find your current consumption by running a DC analysis. If you annotate the DC operating points the current will be displayed. Either use the current stated on the supply voltage source, or sum the currents of your current sources. Then your power consumption is simply P=Vsupply*I.
If a...
Hello JGK,
I design them in triode region too.
Could it be that the senior designer was talking about bipolar transistors where the saturation region would be the equivalent of MOS in triode?
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