Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by lambchops511

  1. L

    PSPICE Parameter Sweep Possible?

    Hi All, I have a current source: Itest0 0 IN0 PULSE(0 2m 0 1u 1u 10m 40m) I want to sweep the delay (i.e. the third parameter) from -40m to 40m ... is that possible w. PSPICE? Thanks. ---------- Post added at 22:21 ---------- Previous post was at 21:18 ---------- kk. found it . the syntax...
  2. L

    Large Capacitors on IBM 180nm HV

    Hi All; I am using IBM 180nm HV -- a marketing spec sheet available from IBM is: ftp://public.dhe.ibm.com/common/ssi/ecm/en/tgd03019usen/TGD03019USEN.PDF Is there any drawbacks (other than area) of making large caps? i.e. 100pF to 1nF range? Would it affect the parasitics of my other devices...
  3. L

    Lower a Current Signal

    hi goldsmith thank you for your reply. what do you mean by "hartley current source"? google did not turn up anything except for the "hartley oscillatory" Do you mean replace my variable resistor and voltage supply w. this current source? I can not replace this -- this is an external component...
  4. L

    Lower a Current Signal

    Suppose I have a current signal coming through a variable resistor .. i.e. the variable resistor is attached to a voltage source and my output is the other end of the variable resistor. The current signal is on the order of magnitude of 1mA ... how would I scale it down to an order of magnitude...
  5. L

    Multiple VDD -- transition from one VDD to another.

    I'm trying to use: **broken link removed** however its not working and I cant seem to find out the problem... for the "Level Translating Block" ... the Body Connections for the PMOS -- should they connect to the Vccb as well right? ---------- Post added at 09:10 ---------- Previous post was...
  6. L

    Multiple VDD -- transition from one VDD to another.

    the schematic you drew... i don't think it will work if i go from 1.8V to say 15V VDD correct? I am actually using 15V VDD in my second circuit (using IBM 180 HV allows up to 50 V). Thanks.
  7. L

    Multiple VDD -- transition from one VDD to another.

    thank you. I guess there is no more efficient to do it... Because I have many of these signals that need to be converted. Thanks.
  8. L

    Multiple VDD -- transition from one VDD to another.

    I am using CMOS IBM 180nm (High Voltage Option) I have two parts of the circuit... A and B A is VDD 1.8 B is VDD 5 A drives logic which will signal something to be B to do something... How would I implement this? How do I transition from VDD 1.8 to VDD 5? Can I just change the body...
  9. L

    TSMC 350nm High Vt Transistor

    I cant find anything on the MOSIS website-- but is there a high Vt transistor available on the TSMC 350nm? I've been using: MOSIS file tsmc-035/t5bp_3_mm_epi-params.txt as my Transistor model If there is a High Vt Transistor option available.. where would I find such a SPICE model? Thanks...
  10. L

    TSMC 350nm (High Voltage) VDD

    Ah- Thank you. I am still on the SPICE simulation at this stage-- havent gotten the PDK yet. Thanks.
  11. L

    TSMC 350nm (High Voltage) VDD

    Sorry-- this is really my first time working on fab-ing something.. What do you mean by "correct device" -- is this something I do in Cadence? Or is this something I do as a checkbox when I submit it to MOSIS later? Many thanks.
  12. L

    TSMC 350nm (High Voltage) VDD

    The link is: TSMC CL035HV Process Is this correct-- this high voltage process can use 15V for VDD? Thanks.
  13. L

    [MOVED]TSMC CMOS 180nm Maximum VDD

    thanks for the reply. seems like I need to use 350nm for the 5V vdd.
  14. L

    [MOVED]TSMC CMOS 180nm Maximum VDD

    whoops. i had a typo in the original post . I meant L=250nm not W=250nm. How would I ask the foundry? Like find a contact email on TSMC website?
  15. L

    [MOVED]TSMC CMOS 180nm Maximum VDD

    Hi all, I am designing for the TSMC 180nm. What is the maximum VDD I can use? If I make my transistor width to 250nm, can I increase my VDD? or would I have to use the TSMC 250nm process for that? Generally, if I use TSMC 180nm, but I create some of my transistors as L=250nm, then I can...
See more

Part and Inventory Search

Back
Top