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Kindly if you can elaborate on what is a DE1 board may be can get some help.
Is it a FPGA board ?
WBR
Lakshman
PS : This Code is from Looks familiar to the one in the book on verilog by samir planitkar
Hi,
All the problems mentioned in the above query and replies have been addressed in this paper from sunburst designs.
Speed of Clock ( write and read domains), underflow conditions, avoiding of read when empty, write when full conditions ... are addressed by the paper i the attachment.
I...
define multi-cycle instruction
How do you synthesize circuits have a generated clock (like a asynchronous circuit )in encounter RC?
sol : the constraint file which is provided during synthesis, must contain the "create generated clock" constraint !
IMHO, generated clock comes into picture...
rtl : it will ur code .v/.vhdl
rtl netlist : its the output of the synthesis process for which rtl will be the input
gate - level - netlist : ur design in the form of gates ( std cell provided by the foundry) only
FOA if u have bought the IP frm some1 els, u cannot specify a input/output delay on those ports !
U have to consult the person who designed tht IP !
ur question : "Could Anybody answer my question: how to add input/output delay constraints on input/output ports of IP who connect external...
ocv
the derating percent to be set would be a flat 10% !
Added after 1 minutes:
For more details abt OCV, the PT manual is the bset to refer !
Its explained in detail in the PT manuls with Examples :-) !!
jus brwse thru the forum for hte PT manuls in case u dnt have !
timing doubt
yes there mite be scenario like the one u ahve mentioned ..... cos setup and hold time are independent of each other(u must be knowing this ! )
hold time will be checked at the same clock edge and setup will be checked at the next clock edge.
positive and negative slack
hey,
"negative slack means .....is it -ve slack means -ve setup or -ve hold ? "
negative slack cn occur both for setup and hold !
When u perform setup analysis, if your arrival time ( Tcq + Tcombi) is greater than required time ( Clock Period- Tsu), then u get...
STA-- no clock registers
hi,
do u have ne generated/divided clocks in ur design ?
if so have u declared them as generated clocks ?, cos if u havnt delcared them, then those registers wil not be getting clocks while ur are doin the STA
and second senario is when u have multiple clocks in ur...
But how does Performing a Setup analysis with BC lib and hold analysis with WC lib help ?
What are the advantages of performing a Four corner analysis ? Ne kinda documents related to the same if uploaded will be relli useful !
To all the Masters of STA ... has anybody performed the same kinda...
what is a four corner analysis ?
i hope every1 is familiar with 2 corner analysis ( setup analysis performed with WC lib & hold analysis performed BC lib) ...
Now is it required to do the setup analysis with BC lib and hold analysis with WC lib as well ? ..... Is this called four corner...
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