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Recent content by kyttaylor

  1. kyttaylor

    SNR calculation in Matlab for a 10-bit Pipeline ADC

    Thanks a lot. I figured the digital correction logic from this **broken link removed**. And I was able to calculate the SNR.
  2. kyttaylor

    SNR calculation in Matlab for a 10-bit Pipeline ADC

    Hi, I designed a 10-bit pipeline ADC with nine 1.5-bits stages in Cadence. As you may very well already know, each 1.5-bits stage has a 2-bit digital output (AB = 00 or 01 or 10). So I exported all the digital outputs from all 9 pipeline stages (i.e. A1B1, A2B2,...., A8B8, A9B9) to Matlab for...
  3. kyttaylor

    How to model a comparator in simulink

    Thanks. I was trying to avoid the sign block. But that would still work
  4. kyttaylor

    How to model a comparator in simulink

    Hi, I've got a comparator with an offset voltage of 10 mV, propagation delay of 40 us, and open loop gain of 70 dB that I need to model in Simulink. Usually, people use the one-input, one-output sign block in simulink as a comparator. But in my case, I need the simulink model of this...
  5. kyttaylor

    How to plot the internal hysteresis loop of a comparator

    Thanks guys :)
  6. kyttaylor

    How to plot the internal hysteresis loop of a comparator

    I don't see how transient analysis would work since it will plot a voltage versus time plot. In contrast, the hysteresis loop, I believe, is a voltage (output) versus voltage (input) plot. That's why I tried a DC sweep, but I can't sweep the input from a positive voltage to a negative.
  7. kyttaylor

    How to plot the internal hysteresis loop of a comparator

    I've got a single-ended comparator, and I need to plot the internal hysteresis loop of this comparator which should look like the attached graph below. How do you perform this simulation on Cadence? Supposing the Ref voltage is ground, I believe I need to DC-sweep the input from let's say from...
  8. kyttaylor

    Switched capacitor circuit design using cadence

    Thanks Pavel :) Added after 2 hours 7 minutes: I also noticed that you get a more accurate frequency response when the clock switching frequency is 100 times greater than the filter cutoff frequency. Can somebody please explain why this is the case? Is it because you have a lot more...
  9. kyttaylor

    Switched capacitor circuit design using cadence

    Hi, Can you guys please tell me how you obtain that PAC frequency response curve with harmonic=0 ??? I don't know how to obtain that graph with the cadence calculator or on the results -> direct plot . Please, drive me through these settings. Thanks
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