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well, It works.
there is another question: If cell A has a hierachical cell B in library lib_a, there is a cell name B in library lib_b too, how could I make the cell B in lib_b priority ( Let Verilog-XL compiler using cell B in lib_b, not the cell B in lib_a)
Thanks & Best Regards
sigma delta applet analog devices
If u want to design or simulate a SD-ADC use Matlab, the Delta Sigma Toolbox by Richard Schreier maybe help.
Summary: High-level design and simulation of delta-sigma...