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Advance Thank's .
Hi every one
1.why matching is used in analog layout design?
as i know to overcome areal and pheripharal errors to maintain voltage same in all the matched transistors
2.is poly resistance is high or metal resistance is high ?
Regard's
Harish
Hi Every One
Can any one explain well proximity effect changes in pmos and nmos what are the difference in them how current effect
1.I came to know that vth is increase if so current decrease is it right
2.device performance effect on oriantaion of source and drain.
Thank You.
Thank's for u reply's
the error which i got is due to connectivity
i raised this question because this type of errors i did not came across
generally connectivity problem gives an property error or net error
but i faced problem with the block which i faced some instantanious errors
but after...
Good after noon
i am facing a problem in analog layout
i design one layout
it is d.r.c and l.v.s cleared
when i am calling that same design it is creating some errors
i checked the file weather any file locks are present but no such locks
can any one help in this problem
Hi
in semi-conductor chips are cleaves from wafers
while cleaving they normally cleave random directions or with help of planes like {100} or {110} or {111} etc ...
Please help.
Thank you.
in 110 nm while running layout drc it is giving as
" N _ WELL WITH DIFFERENT POTENTIAL MUST BE SPRERATTED BY A DIFFERENT DNW_LV_MARK"
I AM USING 6V P_cells IT IS GIVING AT ONLY GAURD RINGS
HOW CAN I SOLVE THIS PROBLEM
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