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Recent content by kumar_eee

  1. K

    Dynamic IR drop analysis

    Perfect Answer.
  2. K

    How to comment out part of a DEF file?

    defOut -noSpecialNet test.def Hope the above command helps.
  3. K

    Design has 600 macros, How will you start the macro placement?

    I was about to say the same. :-D
  4. K

    Timing Checks in primetime

    I prefer the following order. DRV Setup Hold Cross-talk
  5. K

    Query regarding Physical design flow

    Min Latency means more clock-cells, which leads to more clock-tree power. Min skew means all the flops will switch at the same time, which will make your dynamic power to up.
  6. K

    Dynamic IR drop analysis

    Better PG routing, Adding de-cap cells, spread the cells if you're in early stage.
  7. K

    How to use Synopsys saed 28/32 technology file

    I think you can find the tech file inside "tech" folder or something like "starrc".. you will see the file extension like "*.tf"
  8. K

    Where can I get a decent technology library (.db, .sdb) for Synopsys Design Compiler

    I think you misunderstood the concept of target libraries. They are nothing but the same library & will be used by the tool while performing synthesis. Just go through what is link_library & target_library in DC user manual, I'm sure you will get it.
  9. K

    [SOLVED] Endcap and Decap Usage in P&R

    Perfect answer!!!. My comments are below. Process team/Fab comes with certain requirements of well alignments/well rings on layout boundary, if the designer knows the alignment DRC , he can draw well rings/sometimes metal around the boundary to meet process requirements. When these cells are...
  10. K

    Timing Budgeting between Blocks

    I think you should change the clock period in the create_clock definition of block1 clock.
  11. K

    Adding a new net in SoC encounter

    addNet is used to add a net for ECO purpose. If you want to route a net manually, first select the net and shift+A ( add wire ).
  12. K

    what type of adder is used to implement 4bit A+B during synthesis?

    exciting war here!!!... waiting for the final conclusion.
  13. K

    setDesignMode command in encounter

    You should set "setDesignMode", so that the tool can apply certain technology related settings.
  14. K

    How to remove the antenna effect on top metal??

    Two Options are there. 1. Reduce the Higher layer metal area, which means change it to different track. 2. Add the reverse-bias diode at the gate.
  15. K

    45 nm Design rules needed

    check nangate 45nm library, which is freely available.
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