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attached the Schematic, where in though i used Transistors Aspect ratio is identical i am observing slight deviation in current through them as listed below , is that causing the problem of unsymmetrical Vdiff (Vp-Vn) ?
if so how to resolve this ?
below are the operating point...
I have designed (Nmos input current mirror o/p stage) Folded cascode signle ended stage, after doing simulations i have observed different issue like
it can operate over Vcm of 0.75 to 1.8V (as supply vltage is 1.8V)
with this Vcm i am varying Vdiff also to make sure till what value all...
Re: Subthreshold Opamp
which process or technology it is ? and how do u get λN,λP, Kn, Kp is this through set of simulations? how much was there difference u see for your technology from the hand calculation to the actual
circuit similation and results point of view both are same but the difference is one requires(ADE) schematic (there u do connect all voltage sources it is user friendly )
second requires (command line simulations) netlist file , to do this one should know how to mention the voltage sources and...
This kit looks very useful , but i have doubt that why is the V- is connected to 1.5 always? if this is some dc bias voltage how do we arrive on this based on desin?
which is the .print/plot corrensponds to Transient simulation with pulse input?
is this "dcgain" measurement is so called Av(0)...
it does not work pls chk , earlier i had tried with the following lines of statements
but it could not print the .ALTER results where as it printed results related to "model_fast" file
and gave few warnings and stoped