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Respected sir,
i have started working with HSPICE aging analysis and for a given circuit
i got vth degradation for given reltotaltime in the .radeg output file, but for
power gating circuit i want, what will be the lifetime for any
parameter(mainly virtual vdd) degrades 10% or 15% than its...
i need to synthesize verilog analog file of comparator to finally get transistor level netlist, can anyone help me, if it can be done by files provided by ncsu would be better as i have done my earlier work by ncsu provided lib files.
keenly waiting for any reply and thank you in advance
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