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Hello. I have take a module at my university about digital signal processing and my professor gave us two alternatives, a written examination or a project. I think the project is more interesting. But i need to propose to my professor project ideas and he is going to evaluate them. Can you help...
Hello, i have a question about vhdl and unknown values,
I wonder if in structural vhdl we need to write some extra code in order to deal with unknown values.For example in this piece of code:
Agt <= (a and pr_a)or (a and (not b)) or ((not b) and pr_a);
i read somewhere that the and, or, xor...
Hello,
i want to make a structual description of a 4bit comparator using GENERATE stratements.
my code is this:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY temp1 IS
port(Ain,Bin : in std_logic_vector(4 downto 0);
PrevA,PrevB: in std_logic;
AgB, AlB: out...
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