Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
negitive timings in sdf
Neagtive timing check is applied when the Flip Flop or RAM etc whose timing is being constrained contains some logic in addition to the actual synchronous element. By synchronous element I mean the logic that is triggered by clock. An example would be a scan enabled flip...
Re: Clock Design HELP!!!
In the context of a bigger circuit, the method of using multiple clocks to speed up the counter by a fixed factor is not a good one. Introducing a new clock in the design always increases the complexity and affects STA, placement and routing, scan insertion and ATPG...
I dont know if this is what your question was about but ...
1. If the flop has an async reset pin (depends on circuit of flop) then connecting your reset signal to this pin will ensure reset of flop even if the clock is stopped at the time of reset. Also the duration of reset signal (pulse...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
