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verilog bit reverse
i have tried with all those things. It gives illegal part select error. have u tried with that code?
or just putting here
reg [3:0] tmp;
reg [0:3] data;
tmp[3:0]=data[0:3]; //if it is tmp [0:3] it says illegal...
verilog reverse bit order
Can anyone know how to reverse bits in verilog. The code should be simpler (no functions pls and it should be min lines)
Added after 1 hours 8 minutes:
and this is what i wrote
setup hold checks
The time [before the active clock edge] after which any change in the input data could result in the FF latching the wrong value is characterized as the SETUP time of that DFF.
The time [after the active clock edge] for which the DFF output maintains its value before...
some queries reg RHEL5
i am new to linux and i want to know answers to the following
1. how to change monitor frequency like in windows we do my monitor only the 2 freq.s
50 hzs and 60 but in windows they r ranging from 60 to 100 hz
2. how to restore and can we create restore points like...
i dont want the burst duration time or what a sfd contains i want to know what should we send in inter frame gap. special bits ? or something else ? and should i
send only in the first frame or in successive frames
the following code is giving runtime error as "segmentation fault".why?
but the following code is working.................................................