Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The value after the first sync flop will settle to either 0 or 1 when you hit the setup/hold window. This is why the incoming value must be stable for multiple clock B cycles. The correct value will be captured on the next clock B cycle and your logic after the synchronizer will not know or care...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.