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Hi
Please can you advice to me how can i transfer (if it's possible) the HFSS 3D layout design (2D modeler) to to HFSS design (3D modeler)? I would like to at least check (by HFSS design view) if my 2D model representation, port definition etc. in HFSS 3D layout design is corrected setup...
Hi everyone,
Please, can you help me how numeric division between two 1D results in CST MICROWAVE STUODIO could be done? I cant find such option in postprocessing template. Thank you for any advice.
In the case of discrete port: Define a discrete port impedance directly in port setting (only real valued impedance is support).
In the case of waveguide port: Waveguide port generaly needs some homegeneous space in front of propagation wave direction. This is in many case ensured by solver...
You should look at the official CST document: "CST MICROWAVE STUDIO - Workflow and Solver Overview" that you can find it in installation directory or simply used the help. The sensitivity analysis is described on page 113. In short, you must define so-called constraints at first and then setup...
Hi everyone,
I would like to ask you for explanation. I investigated simple (ideal, lossless) microstrip transmission line (MTL) in CST Design Studio (analytical model) with characteristic line impedance approximately 54 Ohm (poor real-valued) and I matched all port reference impedances to this...
Hi all,
I would like to know if the TSMC 90nm transistor models from T-N90-CM-SP-004-K1/T-N90-CM-SP-013-K1 Process Desgin Kit consist reliability parameters for Cadence Reliability Simulator.
Thank you for reactions.
Hi all,
I have a little problem in layout with nch_lvt standard cell. This cell have PDKREC/wellbody Pin layer which defined transistors´s bulk (B) pin. I used Connectivity-Driven capability of Virtuoso design kit to create layout. However I can´t connect this bulk (B) to VSS! net on Metal 1. I...
Hi all,
Please can someone help me with assura to PVS conversion? So how can I convert drc, erc and lvs rule files from one tool to another?
Thanks for your advices.
I am so sorry, you are right ET in europractice means this solution (Encounter Diagnostics Basic,Encounter True Time ATPG Advanced,Option to RC - DFT Architect Advanced). So of course this is not Cadence Encounter Timing System. I downloaded bad tool. Anyway can you help me resolve this problem...
yes the problem was in permission to check that license. I have already fixed it. Thank you very much.
But now i have a problem with Cadence Encounter Timing System tool. When i launch it from terminal by "et" i get library problem:
Encounter(R) Test and Diagnostics 14.1.100 Apr 23, 2014...
Hi all,
Please can you help me solve the following problem? when I start LEC, it immediately crush. This is message what i get after comman "lec":
Command like nmp and ccd work so i really dont know where is the problem. Linux version
Thank you very much for any advice.
Re: Assura,qrc,rcx,pvs (Physical Verification System)
Thank you very much. And PVS product from cadence? A i am interesting mainly about this difference. THANK YOU
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